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Analog Layout
ACL Digital
Hyderabad
Role overview
Job description
Senior Analog Layout Engineer
Location: Hyderabad, Bangalore Experience: 4 to 6 Years Notice Period: Immediate
Job Description: Key Responsibilities Custom Layout Design:
Lead the layout development of critical analog blocks, including
high-speed ADCs/DACs, PLLs, SerDes, Bandgaps, and LDOs . Advanced Node Implementation:
Navigate challenges unique to
sub-3nm nodes , such as multi-patterning, EUV constraints, and FinFET/GAAFET-specific layout-dependent effects (LDE). Physical Verification:
Execute and debug comprehensive verification flows, including
DRC, LVS, ERC, Antenna, and Latch-up
checks using industry-standard tools. Extraction & Analysis:
Perform parasitic extraction (PEX) and collaborate with designers on post-layout simulations to meet stringent timing and performance targets. Floorplanning:
Optimize block-level and top-level floorplans to manage
IR drop, Electromigration (EM), and Thermal-aware placement . Reliability & DFM:
Implement Design for Manufacturability (DFM) guidelines and ensure robust ESD/latch-up protection strategies. Technical Skills & Qualifications Education:
B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or Electrical Engineering. EDA Tools:
Expert proficiency in
Cadence Virtuoso (VXL/GXL)
and
Mentor Graphics Calibre
(DRC/LVS/PEX). Process Experience:
Proven track record with
FinFET technologies
(7nm, 5nm) and direct exposure to
3nm or below
nodes. Analog Fundamentals:
Deep understanding of matching techniques (Common Centroid, Interdigitation), shielding, and isolation (Deep N-Well, Guard Rings). Scripting (Preferred):
Familiarity with
SKILL, Perl, or Tcl
for layout automation and productivity enhancement. Soft Skills Strong problem-solving skills for debugging complex verification errors. Ability to mentor junior engineers and lead small-scale block integrations. Excellent communication skills for collaborating with global cross-functional teams.
Location: Hyderabad, Bangalore Experience: 4 to 6 Years Notice Period: Immediate
Job Description: Key Responsibilities Custom Layout Design:
Lead the layout development of critical analog blocks, including
high-speed ADCs/DACs, PLLs, SerDes, Bandgaps, and LDOs . Advanced Node Implementation:
Navigate challenges unique to
sub-3nm nodes , such as multi-patterning, EUV constraints, and FinFET/GAAFET-specific layout-dependent effects (LDE). Physical Verification:
Execute and debug comprehensive verification flows, including
DRC, LVS, ERC, Antenna, and Latch-up
checks using industry-standard tools. Extraction & Analysis:
Perform parasitic extraction (PEX) and collaborate with designers on post-layout simulations to meet stringent timing and performance targets. Floorplanning:
Optimize block-level and top-level floorplans to manage
IR drop, Electromigration (EM), and Thermal-aware placement . Reliability & DFM:
Implement Design for Manufacturability (DFM) guidelines and ensure robust ESD/latch-up protection strategies. Technical Skills & Qualifications Education:
B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or Electrical Engineering. EDA Tools:
Expert proficiency in
Cadence Virtuoso (VXL/GXL)
and
Mentor Graphics Calibre
(DRC/LVS/PEX). Process Experience:
Proven track record with
FinFET technologies
(7nm, 5nm) and direct exposure to
3nm or below
nodes. Analog Fundamentals:
Deep understanding of matching techniques (Common Centroid, Interdigitation), shielding, and isolation (Deep N-Well, Guard Rings). Scripting (Preferred):
Familiarity with
SKILL, Perl, or Tcl
for layout automation and productivity enhancement. Soft Skills Strong problem-solving skills for debugging complex verification errors. Ability to mentor junior engineers and lead small-scale block integrations. Excellent communication skills for collaborating with global cross-functional teams.